Semiconductor arrangement with a pn transition and method for the production of a semiconductor arrangement

ABSTRACT

A semiconductor system ( 200 ), particularly a diode, having a p-n junction is proposed, that is formed as a chip having an edge area, which includes a first layer ( 2 ) of a first conductivity type and a second layer ( 1, 3 ) of a second conductivity type; the second layer ( 1, 3 ) including at least two sublayers ( 1, 3 ); both sublayers ( 1, 3 ) forming a p-n junction with the first layer ( 2 ); the p-n junction of the first layer ( 2 ) with the first sublayer ( 3 ) being provided exclusively in the interior of the chip, and the p-n junction between the first layer ( 2 ) and the second sublayer ( 1 ) being provided in the edge area of the chip; for each cross-section of the chip area parallel to the chip plane, the first sublayer ( 3 ) corresponding only to a part of such a cross-section.

BACKGROUND INFORMATION

[0001] The present invention is directed to a semiconductor system andto a method according to the definition of the species set forth in thecoordinated independent claims.

[0002] The printed matter DE 4320780 describes a semiconductor diode, inwhich the field intensity occurring in the edge area of thesemiconductor chip is less than the field intensity in the interior ofthe component.

SUMMARY OF THE INVENTION

[0003] In contrast, the semiconductor system of the present inventionand the method of the present invention having the features of thecoordinated independent claims have the advantage that the fieldintensity in the edge area is even further reduced. Moreover, the ratioof the field intensity in the middle of the component to the fieldintensity in the edge area of the component is no longer dependent onthe selected breakdown voltage, the so-called Zener voltage. This inturn has the advantage that even smaller reverse currents may beattained for diodes with unetched edges. The pulse strength, andtherefore the reliability is also further improved. Moreover, it is alsoadvantageously possible to realize diodes with higher breakdown voltagesusing the system of the present invention.

[0004] The measures delineated in the dependent claims render possibleadvantageous embodiments of and improvements to the semiconductor systemand the method for its manufacture recited in the coordinatedindependent claims.

BRIEF DESCRIPTION OF THE DRAWING

[0005] An exemplary embodiment of the present invention is explained indetail in the following description and is shown in the Drawing, inwhich:

[0006]FIG. 1 shows a schematic representation of the cross-section anddoping profile of a known diode;

[0007]FIG. 2 shows a schematic representation of the cross-section anddoping profile of a known diode with reduced marginal field intensity;

[0008]FIG. 3 shows a schematic representation of the cross-section anddoping profile of a first specific embodiment of the semiconductorsystem according to the present invention with reduced marginal fieldintensity;

[0009]FIG. 4 shows a schematic representation of the cross-section anddoping profile of a second specific embodiment of the semiconductorsystem according to the present invention with reduced marginal fieldintensity, in which the patterning is effected by a sawing-in procedure;and

[0010]FIG. 5 shows a schematic representation of the cross-section anddoping profile of a third specific embodiment of the semiconductorsystem according to the present invention with reduced marginal fieldintensity, having additional doping on the chip surfaces.

SPECIFICATION

[0011]FIG. 1 shows a known diode 100 in its cross-section and its dopingprofile. Semiconductor diodes 100 for voltage limitation are as a ruledesigned as p-n diodes, so that a p-doped layer 2, also designated inthe following as first layer 2, is diffused into a homogeneously n-dopedregion 1. To reduce the bulk resistance and for better ohmic binding ofthe n-type semiconductor to the metallization, n-doped region 1 isstrongly n-doped from the back side of the wafer, which in all figures,is to be thought of on the right side of the figure. A region 3designated by reference numeral 3 is thereby formed. N-doped region 1and more strongly n-doped region 3 are also designated jointly in thefollowing as second layer, more strongly n-doped region 3 also beingdesignated as first sublayer 3 of the second layer, and n-doped region 1also being designated as second sublayer 1 of the second layer. Thereference to n-type doping and p-type doping, respectively, for certainlayers or regions is to be understood in FIG. 1 and in all furtherfigures merely by way of example; according to the present invention,the type of charge carrier used for the doping may also be interchanged.

[0012] Diode 100 is shown in the lower part of FIG. 1, and in the upperpart of FIG. 1, a doping profile 110 of diode 100 is shown along a lineextending in a direction perpendicular to the substrate plane of thesemiconductor chip; as in all further figures, the upper side of thesemiconductor chip is shown on the left side of FIG. 1, and thesemiconductor chip, not provided with a reference numeral, is formed byfirst and second layers 1, 2, 3. An upper-side metallization 4 and alower-side metallization 5 are also shown in FIG. 1.

[0013] If a reverse voltage U_(S) is applied to such a diode 100, thecurrent increases sharply as soon as Zener voltage U_(Z) is exceeded.The cause of the current rise, i.e. of the voltage limitation, lies inthe commencing avalanche effect. Upon applying a reverse voltage U_(S),a so-called space charge region develops at the p-n interface, i.e. atthe p-n junction. As of a certain electrical field intensity E_(crit) ofapproximately (2−4)*10⁵ V/cm, charge carriers in the space charge regionare accelerated so strongly that, in response to impacts with thecrystal lattice, they break up bonds of the semiconductor and thusproduce further electrons and holes which, on their part, areaccelerated and are able to break up bonds. In this manner, the currentincreases beyond all measure, that is to say, it can become very great.In the case of known diode 100 according to FIG. 1, the p-n junctionends in the region of a sawing trench in the chip. Namely, to producediodes 100, a plurality of diode chips are produced and processedjointly as a so-called wafer. This plurality of chips must subsequentlybe diced up. This is accomplished, for example, by sawing. The sawingtrenches are thereby formed, which, however, are not designatedindependently in FIG. 1 with a reference numeral, but rather are merelyrecognizable as the edge of the chip. Depending upon the type of saw andthe sawing process, the crystal lattice is disturbed in the region ofthe sawing trenches up to a depth, i.e. in a direction parallel to thechip plane, of several to several tens of micrometers. Such regions,also designated in the following as damage zone, have high densities ofstates in the band gap. The recombination possibility for chargecarriers, and therefore the reverse current thereby increases. Theelectric field intensity necessary to trigger the avalanche effect issubstantially less in the region of the damage zone than in the inner,undisturbed chip region. That is why the avalanche breakdown takes placefirst at the edge of the chip. Resulting from this are pre-breakdownswhich express themselves in rounded blocking-state voltage-currentcharacteristics. Since the current density is therefore increased inthese edge areas, p-n diode 100 is more strongly loaded thermally at thechip edge than in the middle. This results in a markedly reduced pulsestrength of the diode. Therefore, when working with such diodes 100, itis customary to ablate the disturbed chip region, i.e. the damage zone,for example, by etching with KOH. The width of the damage zone isdesignated in FIG. 1 and in all further figures by reference numeral 10.

[0014] Diode 100 disclosed in printed matter DE 4320780 is shown in FIG.2. Here, it is possible to dispense with the etching of the chip edges.Because of the suitable development of the diffusion profiles, the fieldintensity at the chip edge is less than the field intensity in theinterior of the component. In the middle of the chip, a weakly n-dopedlayer 1 a is additionally introduced between p-doped layer 2 and n-dopedlayer 1. Thus, it is possible, for example, to achieve a field intensityE_(R) at the edge of the chip which is less by the factor 2.5 than fieldintensity E_(M) in the interior of the diode chip. Since the reversecurrent of an unetched chip, i.e. of a chip whose damage zone is notremoved, is dependent on the field intensity, the reverse currents in asystem according to FIG. 2 are less in the edge area than in a chipaccording to FIG. 1. A doping profile 110 at the edge of diode 100—i.e.along line of intersection A-B from the lower part of FIG. 1—is shown inthe middle part of FIG. 2, and a doping profile 120 in the middle ofdiode 100—i.e. along line of intersection C-D from the lower part ofFIG. 1—is shown in the upper part of FIG. 2. Plotted in each case—as inall doping profiles shown in the further figures—is the absolute valueof the concentration of the dopants in relative units on an indicatedlogarithmic scale. In the left part of the doping profiles—up to theabsolute minimum of the concentration which marks the change in the typeof charge carrier—the concentration of the first type of charge carrierin first layer 2 of the semiconductor system is shown, andcorrespondingly, the concentration of the second type of charge carrierin the second layer of the semiconductor system is shown in the rightpart of the doping profiles.

[0015] Since for diode 100 of FIG. 2, the breakdown does not take placeat the mechanically and chemically sensitive chip edge, the pulsestrength and the reliability of the diode increases. The systemaccording to FIG. 2 has the disadvantage that the electrical resistanceof the diode in the case of the avalanche breakdown is higher than in asystem according to FIG. 1, since the dopant concentration in theinterior of the chip is very low. This disadvantage becomes even greaterif diodes according to FIG. 2 are to be rated for higher breakdownvoltages U_(Z) than, for example, U_(Z)=25 V. The reverse current alsomay not be reduced arbitrarily, since the relationship of fieldintensities E_(R) to E_(M) is strongly dependent on selected breakdownvoltage U_(Z). If U_(Z) is selected to be higher, the reverse currentincreases.

[0016] The present invention puts forward a simple-to-produce diode 200having reduced marginal field intensity, which eliminates the indicateddisadvantages. Such a diode 200, i.e. such a semiconductor system 200,is shown in FIG. 3 and in the following FIGS. 4 and 5, further specificembodiments of diode 200 from FIG. 3 being depicted in FIGS. 4 and 5.For such a diode 200, the marginal field intensity is even furtherreduced compared to diode 100 shown in FIG. 2. In addition, therelationship of field intensities E_(R) to E_(M) is no longer dependenton selected breakdown voltage U_(Z). Therefore, even smaller reversecurrents may be attained for diodes with unetched edges. The pulsestrength, and therefore the reliability are further improved. At thesame time, the resistance in the avalanche case, i.e. in breakdownoperation of the system, is dramatically reduced. Therefore, accordingto the present invention, it is also possible to realize diodes havinghigher breakdown voltages.

[0017]FIG. 3 shows a schematic representation of the cross-section of afirst specific embodiment of a system 200 according to the presentinvention. First layer 2 is diffused over the entire surface into aweakly n-doped semiconductor substrate from the top side (the left inFIG. 3), and from the other side—in contrast to diode 100 in FIG. 2—apatterned, n-doped first sublayer 3 is diffused into the weakly n-dopedsemiconductor substrate. The upper and lower sides of the chip, i.e. ofthe semiconductor, are provided in known manner with thin metalliclayers 4 and 5. This unpatterned metallization produces the ohmiccontact to the semiconductor. For example, it may be made of the layersequence chromium, nickel, and silver. FIG. 3 also shows the profile ofdopant concentrations 210—along the chip edge; compare line ofintersection A-B from the lower part of FIG. 3—and 220—along the middleof the chip; compare line of intersection C-D from the lower part ofFIG. 3. The n-type doping at the edge—compared to the n-type doping inthe middle—leads to a higher breakdown voltage U_(Z) at the edge than inthe middle region. If a reverse voltage is applied to diode 200, then upto breakdown voltage U_(Z), only the relatively small reverse currentflows which stems essentially from the damage zone. If breakdown fieldintensity E_(crit) is reached in the inner region, the field intensityat edge E_(R) is still very small, since in system 200 of the presentinvention, the ratio of electrical field intensity E_(R) at the edge tofield intensity E_(M) in the middle is large. In turn, this results insmall reverse currents. Since the dopant concentration in the middleregion is substantially greater than for a conventional system, theresistance of the diode is also very small both during operation in theconducting state and in the breakdown state. This system is therebyparticularly suitable for higher Z-voltages U_(Z).

[0018] An advantageous manufacturing process of the present inventionfor a semiconductor system 200 of the present invention is described inFIG. 4 in terms of a second specific embodiment. By way of example,diode 200 is rated for a Zener voltage of approximately 50 V; however,according to the present invention, higher or lower Zener voltages arealso possible.

[0019] A substrate, made in particular of silicon, having a thicknessof, for example, 180 μm, which is provided in FIG. 4 with referencenumeral 50, and having an n-type basic doping of 3.54*10¹⁴ cm⁻³, iscoated, i.e. is doped, on the front side with boron and on the back sidewith phosphorus. Instead of silicon, according to the present invention,another semiconductor material may also be used. The invention isdescribed in the following in terms of a silicon substrate. The basicdoping of the substrate corresponds to the doping of second sublayer 1of the second layer, and is also designated in the following as seconddopant concentration. According to the present invention, thickness 50of the substrate, which corresponds to the thickness of the chip, shouldbe kept as precise as possible and have small tolerances. The coatingmay be accomplished in various ways, for example, by ion implantation,by vapor-phase coating, by doping glasses, by doping pastes or by dopingfoils. In particular, in the present invention, doped glass layers maybe applied by APCVD (atmospheric pressure chemical vapor deposition)methods. Using these methods, boron may advantageously be applied on thefront side and phosphorus may be applied on the back side, virtuallysimultaneously. A diffusion process lasting approximately 0.5 to 3 hoursis subsequently carried out at high temperatures, e.g. at 1265° C., inoxygen-containing atmosphere. After that, for example, a boron dose orphosphorus dose of (1−2)*10¹⁷ cm⁻² is located in the silicon wafer. Thisboron dose or phosphorus dose is concentrated in a comparatively thinlayer, which is also designated in the following as “pre-doping layer”or as pre-coating layer. The n-doped wafer back side, coated withphosphorus, is subsequently patterned. This may advantageously becarried out by sawing into the back side using a diamond saw, or bywater-supported laser cutting. The sawing depth, which is designated inFIG. 4 by reference numeral 20, may, for example, be approximately 10-30μm. As a rule, the sawing depth is selected so that it is deeper thanthe penetration depth of the phosphorus layer at this point of time,i.e. the pre-doping layer. Because of this, in the regions where thephosphorus dose is removed by sawing, the basic doping of the siliconsubstrate is again present. Instead of the sawing, the present inventionalso provides for patterning the back side of the wafer by etching. Byremoving a part of the chip back side, e.g. by sawing, the chipthickness on a partial surface 31 of the back side of the wafer isreduced. On the back side of the wafer which does not belong to partialsurface 31, a type of pedestal is thereby formed in which the phosphorusdose is located. Partial surface 31 therefore becomes a trench comparedto the “pedestal”. According to the present invention, the width of thesaw cut, whose half is designated in FIG. 4 by reference numeral 30, isindicated by way of example at 300 μm. In general, it holds that thesawing width, i.e. its half 30, is selected so that at the end of thesubsequent diffusion process described below, remaining on the waferback side at the chip edge is a region which corresponds to secondsublayer 1, thus where the basic doping of the substrate has remainedunchanged. After the patterning process, the actual diffusion, thedriving of the dopants “stored” in the pre-doping layer into thesemiconductor material, i.e. particularly into the silicon, takes place.This procedure is also denoted as indiffusion. In so doing, secondsublayer 1 is not reached by the “stored” phosphorus dose. Whilecarrying out the diffusion, the phosphorus dose located in the pedestalalso travels into the region of the trench, i.e. partial surface 31,without, however, penetrating it completely. It thereby holds true thatthere is no cross-section of the chip area parallel to the chip plane,for which first sublayer 3 takes up the entire cross-section of thechip.

[0020] Conversely, this means that for each cross-section of the chiparea parallel to the chip plane, first sublayer 3 corresponds only to apart of such a cross-section. According to the present invention, thepatterned “storage” of the dopants for doping the back side of the chipmay of course also be provided in such a way that the doping is carriedout in a patterned fashion, such that the storage of dopants isimplemented in a patterned manner, that is to say, doping is not carriedout on the entire back side of the chip, but rather location-selectivelyonly in the center region of a chip, for example, by conventional phototechniques.

[0021] The diffusion is carried out, for example, at 1265° C. during 142hours. According to the present invention, different diffusiontemperatures and diffusion times, as well as different “stored” doses ofdopants may, of course, also be selected. After the diffusion process, adiffusion profile or a doping profile is obtained as is designated inFIG. 4 by reference numerals 210 and 220, respectively. The diffusionprofile in the actual useful area of the chip, i.e. in the chip center,that is, section C-D, is represented by the concentration profiledesignated by reference numeral 220. The concentration of n-type dopingis greater by several orders of magnitude than at the chip edge; comparethe doping profile, provided with reference numeral 210, alongintersection A-B.

[0022] After the diffusion process, the wafer, having the chips thustreated, is provided in a known manner on its front side and back sidewith metallic layers 4, 5 for the contacting. Thus, the presentinvention provides, for example, for the use of a chromium/nickel/silvermetallization. After the metallization process, the wafers bearing theindividual diode chips are cut through, for example by sawing using, forinstance, a diamond saw having a saw blade width of, for example,

[0023] 40 μm, so that the chips are separated, and the saw-through cutis located precisely in the middle of the wide sawing trench, alreadycreated, for patterning the back side of the wafer. In this context, itis advantageous to saw through the wafer from the back side—representedin the figure on the right side—in order to obtain an easy alignment.The half of the saw blade width is designated in FIG. 4 by referencenumeral 40. Alternatively, it is also provided in the present inventionto separate the chips by water-supported laser cutting or by a chemicalmethod.

[0024] In the present invention, the chips are packaged in a knownmanner in a housing, such as in a diode press-fit housing.

[0025] According to the present invention, particularly to reduce thereverse current even further, it is also possible to remove the damagezone at the chip edge. Methods using wet chemicals (etching, forinstance, with KOH), vapor-phase etching or the like present themselvesfor this purpose. In general, however, this is dispensed with in thepresent invention. In addition, the reverse currents may be diminishedby a temperature treatment of the sawed-through diode chips at 350°C.-500° C. under inert-gas atmosphere or reductive atmosphere.

[0026] If, in the example shown, reverse voltage U_(S) at the diode nowreaches the value of U_(Z)=50 V, then the avalanche breakdown occurs atthe p-n junction between first layer 2 and first sublayer 3. Fieldintensity E_(M) at this interface has reached value E_(crit). Since the“edge diode”, i.e. the p-n junction, present in the edge area of thechip, between first layer 2 and second sublayer 1, would first breakdown, for example, at 640 V, field intensity E_(R) at the edge is verylow in this operating state. For example, it amounts to only a sixth ofthe value in the center of the chip. Therefore, markedly smaller reversecurrents occur than in a system according to FIG. 2. In addition, thisrelationship may be adjusted within wide ranges by varying the basicdoping, which is still present in second sublayer 1, since breakdownvoltage U_(Z) in the chip center is virtually independent of the basicdoping. In contrast to substrate thickness 50, which should have thesmallest possible fluctuations, fluctuations in the basic doping, i.e.in the second dopant concentration, in second sublayer 1 is notcritical. In addition to the small reverse current, a system 200 shownin FIG. 4 exhibits very small bulk resistance and breakdown resistance,since the n-type doping in the useful area, i.e. in the area of sectionC-D, is higher by several orders of magnitude than in the edge area.

[0027]FIG. 5 shows a third exemplary embodiment of system 200 accordingto the present invention, all identical reference numerals from thepreceding figures indicating the equivalent. In the system according toFIG. 5, the region of first layer 2 near to the surface is provided witha flat, strongly p-doped third layer designated by reference numeral 7.In system 200 according to FIG. 5, the regions of first sublayer 3 andof second sublayer 1 near to the surface are likewise provided with aflat, however strongly n-doped fourth layer having reference numeral 6.According to the present invention, third and fourth layers 6, 7 mayagain advantageously be implemented for the front side and the back sidesimultaneously, using one of the doping methods indicated above. Thepenetration depth or the diffusion length of fourth layer 6 on the lowerside is selected so that it is small compared to the thickness of secondsublayer 1 at the chip edge. The surface concentrations of dopants ofthird and fourth layers 6, 7 are selected, according to the presentinvention, in particular to be greater than the associated surfaceconcentrations of dopants of first layer 2 and of first sublayer 3.

[0028] Of course, it is possible according to the present invention tocombine the second and third exemplary embodiments, that is, both topartially take away the surface dose on the back side by sawing as inFIG. 4, and in each case to provide a thin, highly doped third andfourth layer 6, 7 on the front side and back side of the chip, as inFIG. 5.

[0029] According to the present invention, it is also possible to removethe damage zone. This may be done, for example, by etching, particularlyusing wet chemicals, or by gas etching.

What is claimed is:
 1. A semiconductor system (200) having a p-njunction, particularly a diode, which is formed as a chip having an edgearea, comprising a first layer (2) of a first conductivity type and asecond layer (1, 3) of a second conductivity type contrary to the firstconductivity type; the second layer (1, 3) including at least twosublayers (1, 3); the first sublayer (3) having a first dopantconcentration; the second sublayer (1) having a second dopantconcentration; the second dopant concentration being less than the firstdopant concentration; both sublayers (1, 3) forming a p-n junction withthe first layer (2); the p-n junction of the first layer (2) with thefirst sublayer (3) being provided exclusively in the interior of thechip, and the p-n junction between the first layer (2) and the secondsublayer (1) being provided in the edge area of the chip, wherein foreach cross-section of the chip area parallel to the chip plane, thefirst sublayer (3) corresponds only to a part of such a cross-section.2. The semiconductor system (200) as recited in claim 1, wherein thechip is provided in such a way that a dopant for the first sublayer (3)is introduced only in a partial area of the chip surface.
 3. Thesemiconductor system (200) as recited in claim 1, wherein the chip isprovided in such a way that the dopant for the first sublayer (3) ispresent in a patterned fashion.
 4. The semiconductor system (200) asrecited in claim 2 or 3, wherein the first sublayer (3) includes apedestal of the chip.
 5. The semiconductor system (200) as recited inclaim 4, wherein the pedestal is produced by trenches.
 6. Thesemiconductor system (200) as recited in claim 5, wherein the trenchesare produced by sawing, particularly using a diamond saw, or bywater-supported laser cutting.
 7. The semiconductor system (200) asrecited in one of the preceding claims, wherein the semiconductor system(200) includes a third layer (7) and a fourth layer (6), the third andfourth layers (6, 7) having dopant concentrations which are above thoseof the other layers (1, 2, 3).
 8. A method for producing a semiconductorsystem (200) as recited in one of the preceding claims.
 9. The method asrecited in claim 7, wherein the doping is attained by pre-coating andsubsequent indiffusion.